EDN

Next-generation Verilog rises to higher abstraction levels

SAN JOSE, Calif. — A radically revised Verilog language took shape at the International HDL Conference here, as presenters unveiled a language reaching toward much higher levels of abstraction.
EDN

Using SystemVerilog for functional verification

The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

Indeed, designers have embraced SystemVerilog—it's by far the fastest growing design/verification language in the world today (Fig. 1). "The ability to do assertions is significantly improved in ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog?

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...