IEEE

Topology-Aware Graph Neural Network-Based State Estimation for PMU-Unobservable Power Systems

Abstract: Traditional optimization-based techniques for time-synchronized state estimation (SE) often suffer from high online computational burden, limited phasor measurement unit (PMU) coverage, and ...
The Manila Times

MicroCloud Hologram Inc. Develops Serial-Parallel Architecture-Based FPGA Quantum Computing Simulation Framework

MicroCloud Hologram Inc. (NASDAQ: HOLO), ('HOLO” or the 'Company'), a technology service provider, launched a brand-new FPGA-based quantum computing simulation framework founded on a serial-parallel ...
Hackaday

A Compact, Browser-Based ESP32 Oscilloscope

An oscilloscope is usually the most sensitive, and arguably most versatile, tool on a hacker’s workbench, often taking ...
Opinion

The 3D-Flow Architecture Breakthrough: A Universal, Scalable Digital Processor for Real-Time Pattern Recognition in High-Rate Data Streams — A Platform to Save Millions of ...

Worse, the most recent CERN implementation of the FPGA-Based Level-1 Trigger planned for the 2026-2036 decade is a 650 kW system containing an incredibly high number of transistor, 20 trillion in all, ...
GitHub

Ultra-Low-Latency Market Data Parser on FPGA

This project is a sophisticated web monitoring dashboard designed for ultra-low-latency market data parsing systems implemented on FPGA hardware. Built with Next.js 15 and React 19, it provides ...
IEEE

Implementation of a Compact and Resource-Efficient 32-bit Microcontroller Based on RISC-V Steel on FPGA and ASIC

Abstract: This paper presents the implementation and verification process of a 32-bit microcontroller using the open-source RISC-V Steel 32-bit processor on the FPGA DE2 development kit and ASIC ...